Copyright © 1996, 2001 by Thomas L. Iddings

Thomas L. Iddings

President
ECL Advantage, Inc.
1022 East Evelyn Avenue
Sunnyvale, CA 94086
Email: tiddings@ieee.org
VoiceMail and Pager: (408) 381-2194 Fax: (408)248-0781

Very high speed digital circuits, design & modeling, 100 MHz & up

Areas of specialization include:

ASICs and PCB designs in ECL, CMOS, & GaAs Digital

clock generation and distribution to 3 GHz

cable electrical specifications for high performance

SPICE simulations of backplane data distributions

trouble shooting, including signal integrity issues

customize/teach high speed design rules for teams

guidance in the use of Motive Timing Analysis tools

PCB fabrication specifications, routing rules, design reviews

auto-routing control file specifications

prototypes designed, built, and tested

Background: Eighteen years experience in ECL design and test, mixed with CMOS and GaAs Digital. Primarily, applications were in computer image generation, automatic test equipment, and test and instrumentation processes. Significant accomplishments include:

design and test of low noise clock and data distributions in large and small systems, at clock rates over 200 MHz., which worked right the first time!

an 800 MHz. BIST burst clock generator

a 2 GHz logic analyzer

a 1.2 GHz. pattern generator for ATE

Experience includes several instances of:

ECL gate array ASIC design

off-the-shelf GaAS Digital design

controlled impedance embedded resistor PCB design and test

signal integrity analysis

teaching of customized very high speed design rules

SPICE simulations

BSEE, University of California